{"metadata":{"name":"semiconductor-manufacturing","description":"Comprehensive ontology of semiconductor manufacturing \u2014 covering fabrication processes, materials, equipment, business models, chip types, transistor architectures, packaging, metrology, and the global supply chain"},"nodes":[{"id":"n_MNHupChPrcl3","type":"FabricationProcess","properties":{"name":"Wafer Preparation","description":"Slicing pure silicon ingots into thin wafers and polishing to extreme smoothness, eliminating impurities and scratches","stage":"front-end","key_steps":"crystal growth, slicing, lapping, polishing, cleaning"}},{"id":"n_z1kKDbfxpUgX","type":"FabricationProcess","properties":{"name":"Oxidation","description":"Spraying oxygen or water vapor on wafer surface to form uniform silicon dioxide film for insulation and protection","stage":"front-end","methods":"dry oxidation, wet oxidation, thermal oxidation"}},{"id":"n_-NTH5w0N6xSc","type":"FabricationProcess","properties":{"name":"Photolithography","description":"Transferring circuit patterns from a photomask onto a photoresist-coated wafer using light exposure","stage":"front-end","key_steps":"photoresist coating, alignment, exposure, development"}},{"id":"n_pfomrDa8oYtd","type":"FabricationProcess","properties":{"name":"Etching","description":"Selectively removing material from the wafer surface to create circuit patterns defined by photolithography","stage":"front-end","types":"wet etching, dry etching, plasma etching, reactive ion etching (RIE)"}},{"id":"n_lmb6kT5QIK0T","type":"FabricationProcess","properties":{"name":"Deposition","description":"Depositing thin films of materials onto the wafer surface to build up circuit layers","stage":"front-end","types":"CVD, PVD, ALD, epitaxy, sputtering, evaporation"}},{"id":"n_QA79JhsG_ycr","type":"FabricationProcess","properties":{"name":"Ion Implantation","description":"Accelerating dopant ions into the silicon substrate to modify electrical properties and create p-type or n-type regions","stage":"front-end","dopants":"boron (p-type), phosphorus (n-type), arsenic (n-type)","follow_up":"thermal annealing required to activate dopants"}},{"id":"n_Tctx18kbrk8n","type":"FabricationProcess","properties":{"name":"Diffusion","description":"Introducing dopant atoms from gas phase or doped-oxide sources at high temperature to create deep junctions","stage":"front-end","complements":"ion implantation for shallow junctions"}},{"id":"n_vWDzWZb3pTrr","type":"FabricationProcess","properties":{"name":"Metallization","description":"Depositing thin metal films (aluminum, copper, tungsten, titanium) to create electrical interconnects between transistors","stage":"front-end","materials":"aluminum, copper, tungsten, titanium, cobalt"}},{"id":"n_pRnpZ0bqU4uE","type":"FabricationProcess","properties":{"name":"Chemical Mechanical Planarization (CMP)","description":"Polishing wafer surface using chemical slurry and mechanical abrasion to achieve global planarity between process layers","stage":"front-end"}},{"id":"n_bmaJ3kGme_cq","type":"FabricationProcess","properties":{"name":"Wafer Testing","description":"Electrical testing of individual dies on the wafer before dicing, applying voltage to each component and measuring performance","stage":"back-end","alias":"wafer probing, wafer sort"}},{"id":"n_8QbkNS7wO_0S","type":"FabricationProcess","properties":{"name":"Dicing","description":"Cutting individual dies (chips) from the completed wafer using diamond saws or laser cutting","stage":"back-end"}},{"id":"n_h7HMcZglsMjr","type":"FabricationProcess","properties":{"name":"Packaging","description":"Encasing the die in a protective package with electrical leads for connection to circuit boards","stage":"back-end","types":"wire bonding, flip chip, BGA, QFP, CSP, fan-out wafer-level packaging"}},{"id":"n_BXz1CkMAan0w","type":"FabricationProcess","properties":{"name":"Final Testing","description":"Comprehensive electrical and functional testing of packaged chips under various conditions before shipment","stage":"back-end"}},{"id":"n_HSn13am7kSrA","type":"DepositionTechnique","properties":{"name":"Chemical Vapor Deposition (CVD)","description":"Gaseous precursors react and decompose on heated substrate to form thin films. Step coverage >95%. Used for dielectrics like SiO2 and Si3N4","variants":"LPCVD, PECVD, MOCVD, APCVD"}},{"id":"n_LhB-Ec3-lLsg","type":"DepositionTechnique","properties":{"name":"Physical Vapor Deposition (PVD)","description":"Material transferred from source to substrate through physical processes like sputtering or evaporation. Higher deposition rates, superior film homogeneity","variants":"sputtering, e-beam evaporation, thermal evaporation"}},{"id":"n_cKli_MLoaxra","type":"DepositionTechnique","properties":{"name":"Atomic Layer Deposition (ALD)","description":"Layer-by-layer deposition using sequential self-limiting reactions. Superior thickness control at 0.1-0.2 nm/cycle. Can coat structures with aspect ratios >100:1","tradeoff":"slow throughput but exceptional uniformity"}},{"id":"n_Nm8Ly_pUJ0hL","type":"DepositionTechnique","properties":{"name":"Epitaxy","description":"Growing thin films with the same crystalline structure as the substrate. Critical for creating high-quality semiconductor layers","variants":"MBE (molecular beam epitaxy), VPE (vapor phase epitaxy)"}},{"id":"n_9e82HgilShxv","type":"EtchingTechnique","properties":{"name":"Wet Etching","description":"Using liquid chemical solutions (acids/bases) to dissolve material. Isotropic profile. Simple but less precise","chemicals":"HF, KOH, H3PO4, buffered oxide etch"}},{"id":"n__tan2DG0WFNb","type":"EtchingTechnique","properties":{"name":"Dry Etching","description":"Using ionized gases/plasma to remove material. Anisotropic profile enables high aspect ratio structures. Dominant in modern fabs","variants":"plasma etching, reactive ion etching (RIE), deep reactive ion etching (DRIE)"}},{"id":"n_yw3tYYxrlUu5","type":"EtchingTechnique","properties":{"name":"Reactive Ion Etching (RIE)","description":"Most important etch process in semiconductor manufacturing. Chemically reactive plasma removes material with precise anisotropic control. Both chemical and physical etch mechanisms","gases":"CF4, SF6, Cl2, BCl3, CHF3"}},{"id":"n_oe5_o2dEcI3x","type":"LithographyTechnology","properties":{"name":"Deep Ultraviolet Lithography (DUV)","description":"Uses 193nm wavelength light. Enables features down to ~40nm. Mature and widely deployed technology. Uses ArF (argon fluoride) excimer lasers","enhancement":"immersion lithography, multiple patterning"}},{"id":"n_rt3mYOzNV_mk","type":"LithographyTechnology","properties":{"name":"Extreme Ultraviolet Lithography (EUV)","description":"Uses 13.5nm wavelength from laser-pulsed tin plasma. Enables features <20nm. ASML is sole manufacturer. Required for 7nm and below","cost":"$150M+ per system","key_challenge":"source power, mask defectivity, photoresist sensitivity","_starred":true}},{"id":"n_PPPc4s3RDj0j","type":"LithographyTechnology","properties":{"name":"High-NA EUV","description":"Next-generation EUV with higher numerical aperture (0.55 vs 0.33) for sub-2nm nodes. ASML TWINSCAN EXE:5000 platform","resolution":"8nm half-pitch capability"}},{"id":"n_f8WecSRnA6Oo","type":"TransistorArchitecture","properties":{"name":"Planar MOSFET","description":"Traditional flat transistor with gate on top of channel. Gate contacts channel on one side. Dominant until ~22nm node. Suffers short-channel effects below 20nm"}},{"id":"n_pufyoer4s25B","type":"TransistorArchitecture","properties":{"name":"FinFET","description":"3D transistor with fin-shaped channel. Gate wraps around channel on three sides. Commercialized in early 2010s. Dominant from 16nm to 5nm nodes","first_commercial":"Intel 22nm (2012)","limitation":"variability increases at 3nm and below"}},{"id":"n_REw7AnTtUDcG","type":"TransistorArchitecture","properties":{"name":"Gate-All-Around FET (GAAFET)","description":"Gate wraps around channel on all four sides using stacked nanosheets. Superior electrostatic control. Successor to FinFET at 3nm and below","structure":"stacked nanosheet/nanowire silicon channels","adopters":"Samsung (3GAA, 2022), TSMC (N2, 2025)"}},{"id":"n_tor6YhdUgK_T","type":"TransistorArchitecture","properties":{"name":"Complementary FET (CFET)","description":"Stacks NMOS and PMOS transistors vertically on top of each other. Potential successor to GAAFET. Being researched for sub-1nm nodes","status":"R&D stage"}},{"id":"n_7LBwQX7mAFew","type":"EquipmentCompany","properties":{"name":"ASML","headquarters":"Netherlands","specialty":"Photolithography systems (DUV and EUV)","market_position":"100% monopoly on EUV lithography. Largest semiconductor equipment company by market cap","key_products":"TWINSCAN NXE (EUV), TWINSCAN EXE (High-NA EUV), TWINSCAN NXT (DUV)"}},{"id":"n_jgHDJRey5Ixp","type":"EquipmentCompany","properties":{"name":"Applied Materials","headquarters":"USA","specialty":"Broad portfolio: deposition, etching, CMP, ion implantation, inspection","market_position":"Largest semiconductor equipment company by revenue after ASML. One-stop-shop strategy","revenue_2023":"$26.5B"}},{"id":"n_FNqc3Rcs2U9V","type":"EquipmentCompany","properties":{"name":"Lam Research","headquarters":"USA","specialty":"Etch, deposition, and clean systems","market_position":"Leading provider of wafer fabrication equipment for etch and deposition"}},{"id":"n_VvR8_G16XiWn","type":"EquipmentCompany","properties":{"name":"Tokyo Electron (TEL)","headquarters":"Japan","specialty":"Coater/developers, etch, deposition, cleaning, and test systems","market_position":"Largest semiconductor equipment company in Japan"}},{"id":"n_GmVtLr1067-v","type":"EquipmentCompany","properties":{"name":"KLA Corporation","headquarters":"USA","specialty":"Metrology, inspection, and process control systems for defect detection","key_products":"Bright-field inspection, e-beam review, CIRCL wafer inspection cluster, scatterometry","capabilities":"Sub-nanometer precision, defects down to 1-3nm detection"}},{"id":"n_17RJxxu-1biD","type":"EquipmentCompany","properties":{"name":"ZEISS SMT","headquarters":"Germany","specialty":"Optics and mirror systems for EUV lithography. Exclusive supplier to ASML for EUV optics"}},{"id":"n_J7A8W6zPDREw","type":"Foundry","properties":{"name":"TSMC","headquarters":"Taiwan","market_share":"64% of global foundry market (2024)","advanced_nodes":"3nm (N3, 2022), 2nm (N2 GAA, 2025)","description":"World's largest dedicated semiconductor foundry. Most critical single point in the semiconductor supply chain"}},{"id":"n_6StRjGGxeqRQ","type":"Foundry","properties":{"name":"Samsung Foundry","headquarters":"South Korea","market_share":"12% of global foundry market (2024)","advanced_nodes":"3nm GAA (3GAA, 2022), 2nm (SF2, late 2025)","description":"First to ship GAA transistors at 3nm. Also an IDM with memory leadership"}},{"id":"n_QlZFfoES8c-u","type":"IDM","properties":{"name":"Intel","headquarters":"USA","description":"Pioneered FinFET commercialization at 22nm (2012). Operates Intel Foundry Services. Largest Western chipmaker","advanced_nodes":"Intel 4, Intel 3, Intel 20A (RibbonFET GAA)","market_share":"<5% foundry market"}},{"id":"n_IH1MmaoZXgaY","type":"IDM","properties":{"name":"Texas Instruments","headquarters":"USA","specialty":"Analog and embedded processing chips","description":"World's largest analog semiconductor company. Operates own fabs focused on mature nodes"}},{"id":"n_JBQ9OBRjp70o","type":"FablessCompany","properties":{"name":"Qualcomm","headquarters":"USA","specialty":"Mobile SoCs, 5G modems, wireless chips","foundry_partner":"TSMC, Samsung"}},{"id":"n_DBJ0urA3VtIk","type":"FablessCompany","properties":{"name":"AMD","headquarters":"USA","specialty":"CPUs, GPUs, data center processors","foundry_partner":"TSMC"}},{"id":"n_ZTSzJ-ebtciO","type":"FablessCompany","properties":{"name":"Apple","headquarters":"USA","specialty":"Custom SoCs for iPhone, iPad, Mac (A-series, M-series)","foundry_partner":"TSMC"}},{"id":"n_TX847Of2SeJs","type":"OSAT","properties":{"name":"ASE Group","headquarters":"Taiwan","description":"World's largest OSAT provider. Semiconductor packaging, assembly, and testing services"}},{"id":"n_Nmb_jsEFM7ji","type":"OSAT","properties":{"name":"Amkor Technology","headquarters":"USA","description":"Second largest OSAT provider. Advanced packaging including 2.5D/3D integration"}},{"id":"n__sKPJhqMpzUJ","type":"Material","properties":{"name":"Silicon","description":"Primary substrate material for ~95% of semiconductor wafers. Grown as single-crystal ingots via Czochralski process","purity":"99.9999999% (9N) for electronic grade silicon"}},{"id":"n_oMAWJfokYYz1","type":"Material","properties":{"name":"Silicon Dioxide (SiO2)","description":"Key dielectric/insulating layer grown by thermal oxidation. Used as gate oxide and isolation layer"}},{"id":"n_yKCa6KKlidl7","type":"Material","properties":{"name":"Photoresist","description":"Light-sensitive polymer coated on wafers for photolithography. Positive resist (exposed areas dissolve) and negative resist (exposed areas harden)","solvents":"glycol ethers"}},{"id":"n_oSGWGfFn0kC5","type":"Material","properties":{"name":"Copper","description":"Primary interconnect metal in modern chips since 130nm node. Lower resistance than aluminum. Deposited via electroplating after barrier/seed layers"}},{"id":"n_djF4CuPp7RDX","type":"Material","properties":{"name":"High-k Dielectrics","description":"Materials like hafnium oxide (HfO2) replacing SiO2 as gate dielectric at 45nm and below. Higher dielectric constant reduces leakage current"}},{"id":"n_CSj9ynuSx88I","type":"Material","properties":{"name":"Silicon Germanium (SiGe)","description":"Alloy used in strained silicon channels and GAAFET nanosheet structures. Enables strain engineering for improved carrier mobility"}},{"id":"n_7jYLNIOjYuOj","type":"Material","properties":{"name":"Gallium Arsenide (GaAs)","description":"III-V compound semiconductor used in ~5% of wafers. Higher electron mobility than silicon. Used in RF, optoelectronics, and high-speed applications"}},{"id":"n_qLiLlSbxddBq","type":"SpecialtyGas","properties":{"name":"Silane (SiH4)","description":"Primary precursor gas for CVD deposition of silicon and silicon-based thin films"}},{"id":"n_0mb34d39utPP","type":"SpecialtyGas","properties":{"name":"Fluorine-based Etchants","description":"CF4, SF6, NF3 used for etching silicon and silicon dioxide. Critical for dry etch processes"}},{"id":"n_LETJSJQTIFq6","type":"SpecialtyGas","properties":{"name":"Chlorine-based Etchants","description":"Cl2, BCl3, HCl used for etching metals like aluminum and for III-V semiconductor processing"}},{"id":"n_EgrxpPpKGa4b","type":"ChipType","properties":{"name":"DRAM","category":"Memory - Volatile","description":"Dynamic Random Access Memory. Each bit stored in capacitor+transistor. Requires periodic refresh. Used in computers, servers, smartphones","key_makers":"Samsung, SK Hynix, Micron"}},{"id":"n_P7og2v-Fw67G","type":"ChipType","properties":{"name":"NAND Flash","category":"Memory - Non-Volatile","description":"Non-volatile storage. Higher data density, lower cost. Used in SSDs, USB drives, SD cards. 3D NAND stacks layers vertically for density","key_makers":"Samsung, SK Hynix, Kioxia/WD, Micron"}},{"id":"n_-GtfhpMAJZGL","type":"ChipType","properties":{"name":"SRAM","category":"Memory - Volatile","description":"Static Random Access Memory. Faster than DRAM, no refresh needed. Uses 6 transistors per bit. Used for CPU caches"}},{"id":"n_I65yRBleQf6r","type":"ChipType","properties":{"name":"Logic Chip (CPU)","category":"Logic","description":"Central processing unit. General-purpose processor for computation. Complex instruction sets (x86, ARM)","key_makers":"Intel, AMD, Apple, Qualcomm"}},{"id":"n_yDp1GdxqwN3L","type":"ChipType","properties":{"name":"GPU","category":"Logic","description":"Graphics processing unit. Massively parallel processor. Originally for graphics, now essential for AI/ML training and inference","key_makers":"NVIDIA, AMD, Intel"}},{"id":"n_DjIHxI3jj3C0","type":"ChipType","properties":{"name":"Analog IC","category":"Analog","description":"Processes continuous signals (sound, temperature, light). Interfaces between digital systems and real world. Power management, signal conversion","key_makers":"Texas Instruments, Analog Devices, Infineon"}},{"id":"n_HMok8MMxIa6k","type":"ChipType","properties":{"name":"Power Semiconductor","category":"Discrete","description":"Manages and converts electrical power. MOSFETs, IGBTs, diodes. Critical for EVs, industrial, and renewable energy","key_makers":"Infineon, ON Semiconductor, STMicroelectronics"}},{"id":"n_8swsPTpSCTEN","type":"ChipType","properties":{"name":"SoC (System on Chip)","category":"Logic","description":"Integrates CPU, GPU, memory controller, I/O, and other functions on a single die. Dominant in mobile and embedded applications","examples":"Apple A-series/M-series, Qualcomm Snapdragon"}},{"id":"n_2ZHsneCXHzIa","type":"PackagingTechnology","properties":{"name":"Wire Bonding","description":"Traditional interconnection using thin gold/copper wires between die pads and package leads. Mature, cost-effective, reliable. Dominant in power and automotive electronics"}},{"id":"n_rv6vr2ljvNqW","type":"PackagingTechnology","properties":{"name":"Flip Chip","description":"Die is flipped and connected face-down using solder bumps. Shorter interconnects, better electrical/thermal performance than wire bonding. Mainstream for high-performance chips"}},{"id":"n_vP0lE-sIUcmE","type":"PackagingTechnology","properties":{"name":"2.5D Packaging","description":"Multiple dies placed side-by-side on a silicon interposer with through-silicon vias (TSVs). Enables heterogeneous integration of different chip types","examples":"TSMC CoWoS, AMD EPYC"}},{"id":"n_wT22RZ2AWhNE","type":"PackagingTechnology","properties":{"name":"3D Packaging","description":"Stacking active dies vertically with TSVs or hybrid bonding. Highest integration density. Used in HBM memory stacks and advanced processors","examples":"HBM (High Bandwidth Memory), 3D NAND"}},{"id":"n_75YQN8G1UadR","type":"PackagingTechnology","properties":{"name":"Chiplet Architecture","description":"Multiple smaller dies (chiplets) within a single package. Improves yield, lowers cost, enables mix-and-match of different process nodes and IP blocks","examples":"AMD Zen CPUs, Intel Ponte Vecchio","standard":"UCIe (Universal Chiplet Interconnect Express)"}},{"id":"n_tR9WmbjomEui","type":"PackagingTechnology","properties":{"name":"Hybrid Bonding","description":"Cu-Cu bumpless bonding achieving sub-10\u03bcm pitch. Direct copper-to-copper connection between stacked dies. Emerging as key enabler for 3D integration"}},{"id":"n_Dqsg-ApIliOR","type":"PackagingTechnology","properties":{"name":"Fan-Out Wafer Level Packaging (FOWLP)","description":"Redistribution layers extend I/O connections beyond die edge. Thinner profile, better thermal performance. Used in mobile and IoT applications","examples":"TSMC InFO"}},{"id":"n_9tEU1emzCl6v","type":"Facility","properties":{"name":"Semiconductor Fab (Cleanroom)","description":"Ultra-clean manufacturing facility for wafer fabrication. ISO Class 1-5 cleanroom. ULPA filters, controlled temperature (20-22\u00b0C) and humidity (\u00b11-2% RH)","cost":"$10-20+ billion for leading-edge fab","construction_time":"2-4 years"}},{"id":"n_uuYLPx8y0H-M","type":"ProcessNode","properties":{"name":"7nm Node","description":"First node to require EUV lithography. FinFET architecture. TSMC volume production 2018","transistor_type":"FinFET"}},{"id":"n_1pf530zOO_h4","type":"ProcessNode","properties":{"name":"5nm Node","description":"EUV lithography with multiple patterning. FinFET architecture. TSMC/Samsung volume production 2020","transistor_type":"FinFET"}},{"id":"n_TqwmAcZtu2QL","type":"ProcessNode","properties":{"name":"3nm Node","description":"TSMC uses FinFET (N3, 2022). Samsung uses GAAFET (3GAA, 2022). Transition point from FinFET to GAA","transistor_type":"FinFET (TSMC), GAAFET (Samsung)"}},{"id":"n_5HpKwEX3ekmU","type":"ProcessNode","properties":{"name":"2nm Node","description":"Both TSMC and Samsung transitioning to GAAFET/nanosheet. TSMC N2 (2025). Samsung SF2 (late 2025)","transistor_type":"GAAFET (nanosheet)"}},{"id":"n_Qy0MAHKWfUix","type":"ProcessNode","properties":{"name":"Sub-2nm / Angstrom Era","description":"Future nodes exploring CFET (complementary FET), backside power delivery, 2D materials. High-NA EUV required","transistor_type":"CFET, 2D channel materials"}},{"id":"n_tF3-jEypq7hB","type":"BusinessModel","properties":{"name":"IDM (Integrated Device Manufacturer)","description":"Companies that design, manufacture, package, and sell their own chips. Full vertical integration. Own and operate fabs","examples":"Intel, Samsung, Texas Instruments, Infineon"}},{"id":"n_h-upjhD_FuG2","type":"BusinessModel","properties":{"name":"Fabless","description":"Companies that design chips but outsource all manufacturing to foundries. Dominant in high-growth markets (AI, mobile, wireless)","examples":"NVIDIA, Qualcomm, AMD, Apple, Broadcom, MediaTek"}},{"id":"n_g92FZR_HHS2u","type":"BusinessModel","properties":{"name":"Pure-Play Foundry","description":"Manufacture chips on contract for other companies. No competing chip designs. Capital-intensive model requiring $10B+ fabs","examples":"TSMC, GlobalFoundries, UMC, SMIC"}},{"id":"n_QPDGTJ9l2Wtc","type":"BusinessModel","properties":{"name":"OSAT (Outsourced Assembly & Test)","description":"Specialist firms providing backend packaging, assembly, and testing services. >95% located in Indo-Pacific region","examples":"ASE Group, Amkor, JCET"}},{"id":"n_r1q8Ke2fyK9s","type":"MetrologyTechnique","properties":{"name":"Optical Inspection","description":"Bright-field and dark-field optical inspection for wafer-level defect detection. Full-wafer coverage. Resolution limit ~20-30nm"}},{"id":"n_U2-ZT79svbJ7","type":"MetrologyTechnique","properties":{"name":"E-Beam Inspection","description":"Electron beam inspection achieving 1-3nm sensitivity for nanoscale defect detection. Slower throughput than optical but much higher resolution"}},{"id":"n_Uo5jND18Bxra","type":"MetrologyTechnique","properties":{"name":"Scatterometry (OCD)","description":"Optical critical dimension measurement using light scattering patterns. Non-destructive, high-throughput measurement of feature dimensions"}},{"id":"n_rBfosr3gqIGZ","type":"QualityStandard","properties":{"name":"ISO 14644-1","description":"International standard for cleanroom classification. Classes 1-9 based on particle count per cubic meter. Semiconductor fabs typically ISO Class 1-5"}}],"edges":[{"id":"e_AFyoz9b-67un","type":"PRECEDES","sourceId":"n_MNHupChPrcl3","targetId":"n_z1kKDbfxpUgX","properties":{"description":"Wafer Preparation precedes Oxidation in the fab process flow"}},{"id":"e_S9JQxN9VwOOF","type":"PRECEDES","sourceId":"n_z1kKDbfxpUgX","targetId":"n_-NTH5w0N6xSc","properties":{"description":"Oxidation precedes Photolithography"}},{"id":"e_E65awWX1FBfE","type":"PRECEDES","sourceId":"n_-NTH5w0N6xSc","targetId":"n_pfomrDa8oYtd","properties":{"description":"Photolithography precedes Etching"}},{"id":"e_KggGiwBos82m","type":"PRECEDES","sourceId":"n_pfomrDa8oYtd","targetId":"n_QA79JhsG_ycr","properties":{"description":"Etching precedes Ion Implantation"}},{"id":"e_t51v2wN6DarA","type":"PRECEDES","sourceId":"n_lmb6kT5QIK0T","targetId":"n_vWDzWZb3pTrr","properties":{"description":"Deposition precedes Metallization in back-end-of-line"}},{"id":"e_mpWvuXpaXMA-","type":"PRECEDES","sourceId":"n_vWDzWZb3pTrr","targetId":"n_pRnpZ0bqU4uE","properties":{"description":"Metallization precedes CMP planarization"}},{"id":"e_HPqv3QF74N9M","type":"PRECEDES","sourceId":"n_pRnpZ0bqU4uE","targetId":"n_bmaJ3kGme_cq","properties":{"description":"CMP precedes Wafer Testing"}},{"id":"e_TQpwunvgs4co","type":"PRECEDES","sourceId":"n_bmaJ3kGme_cq","targetId":"n_8QbkNS7wO_0S","properties":{"description":"Wafer Testing precedes Dicing"}},{"id":"e_9R_TGR5ejFvk","type":"PRECEDES","sourceId":"n_8QbkNS7wO_0S","targetId":"n_h7HMcZglsMjr","properties":{"description":"Dicing precedes Packaging"}},{"id":"e_-8hKTWroqByx","type":"PRECEDES","sourceId":"n_h7HMcZglsMjr","targetId":"n_BXz1CkMAan0w","properties":{"description":"Packaging precedes Final Testing"}},{"id":"e_6xAaqID3XW-e","type":"TECHNIQUE_OF","sourceId":"n_HSn13am7kSrA","targetId":"n_lmb6kT5QIK0T","properties":{"description":"CVD is a technique used in the Deposition process"}},{"id":"e__HTC3tW-ivUv","type":"TECHNIQUE_OF","sourceId":"n_LhB-Ec3-lLsg","targetId":"n_lmb6kT5QIK0T","properties":{"description":"PVD is a technique used in the Deposition process"}},{"id":"e_UcOvBkPPG9xU","type":"TECHNIQUE_OF","sourceId":"n_cKli_MLoaxra","targetId":"n_lmb6kT5QIK0T","properties":{"description":"ALD is a technique used in the Deposition process"}},{"id":"e_1um5zHsZwd0S","type":"TECHNIQUE_OF","sourceId":"n_Nm8Ly_pUJ0hL","targetId":"n_lmb6kT5QIK0T","properties":{"description":"Epitaxy is a technique used in the Deposition process"}},{"id":"e_XSOuCAqj2k7Z","type":"TECHNIQUE_OF","sourceId":"n_9e82HgilShxv","targetId":"n_pfomrDa8oYtd","properties":{"description":"Wet Etching is a technique used in the Etching process"}},{"id":"e_k3Y0XV6QWXdz","type":"TECHNIQUE_OF","sourceId":"n__tan2DG0WFNb","targetId":"n_pfomrDa8oYtd","properties":{"description":"Dry Etching is a technique used in the Etching process"}},{"id":"e_5RsHhU8sGGiX","type":"VARIANT_OF","sourceId":"n_yw3tYYxrlUu5","targetId":"n__tan2DG0WFNb","properties":{"description":"RIE is a variant of Dry Etching"}},{"id":"e_I4gBBqKq8-UP","type":"TECHNIQUE_OF","sourceId":"n_oe5_o2dEcI3x","targetId":"n_-NTH5w0N6xSc","properties":{"description":"DUV lithography is a technique used in Photolithography"}},{"id":"e_R5CVFD2wYwBK","type":"TECHNIQUE_OF","sourceId":"n_rt3mYOzNV_mk","targetId":"n_-NTH5w0N6xSc","properties":{"description":"EUV lithography is a technique used in Photolithography"}},{"id":"e_PlAQ00jkaPOy","type":"SUCCESSOR_OF","sourceId":"n_PPPc4s3RDj0j","targetId":"n_rt3mYOzNV_mk","properties":{"description":"High-NA EUV is the successor to standard EUV"}},{"id":"e_PZsjmBw_4aE4","type":"SUCCESSOR_OF","sourceId":"n_pufyoer4s25B","targetId":"n_f8WecSRnA6Oo","properties":{"description":"FinFET succeeded Planar MOSFET at 22nm node"}},{"id":"e_4QhflcMtaN5P","type":"SUCCESSOR_OF","sourceId":"n_REw7AnTtUDcG","targetId":"n_pufyoer4s25B","properties":{"description":"GAAFET succeeded FinFET at 3nm node"}},{"id":"e_h-QOuFrM0hvT","type":"SUCCESSOR_OF","sourceId":"n_tor6YhdUgK_T","targetId":"n_REw7AnTtUDcG","properties":{"description":"CFET is the expected successor to GAAFET at sub-1nm nodes"}},{"id":"e_xm9WOPGS1JwC","type":"MANUFACTURES","sourceId":"n_7LBwQX7mAFew","targetId":"n_rt3mYOzNV_mk","properties":{"description":"ASML is the sole manufacturer of EUV lithography systems"}},{"id":"e_VebjBJnZ68Oo","type":"MANUFACTURES","sourceId":"n_7LBwQX7mAFew","targetId":"n_oe5_o2dEcI3x","properties":{"description":"ASML manufactures DUV lithography systems"}},{"id":"e_HfjtiuQ4cmoO","type":"MANUFACTURES","sourceId":"n_7LBwQX7mAFew","targetId":"n_PPPc4s3RDj0j","properties":{"description":"ASML manufactures High-NA EUV systems"}},{"id":"e_LuVDgH-y6Cz8","type":"SUPPLIES_OPTICS_TO","sourceId":"n_17RJxxu-1biD","targetId":"n_7LBwQX7mAFew","properties":{"description":"ZEISS SMT is exclusive supplier of EUV optics to ASML"}},{"id":"e_-KKqlDJolDQ8","type":"PROVIDES_EQUIPMENT_FOR","sourceId":"n_jgHDJRey5Ixp","targetId":"n_lmb6kT5QIK0T","properties":{"description":"Applied Materials provides deposition equipment"}},{"id":"e_MFgBQOyHJYQD","type":"PROVIDES_EQUIPMENT_FOR","sourceId":"n_jgHDJRey5Ixp","targetId":"n_pfomrDa8oYtd","properties":{"description":"Applied Materials provides etching equipment"}},{"id":"e_Q7yHn3xqEHTt","type":"PROVIDES_EQUIPMENT_FOR","sourceId":"n_jgHDJRey5Ixp","targetId":"n_QA79JhsG_ycr","properties":{"description":"Applied Materials provides ion implantation equipment"}},{"id":"e_x_YY-6PffONV","type":"PROVIDES_EQUIPMENT_FOR","sourceId":"n_FNqc3Rcs2U9V","targetId":"n_pfomrDa8oYtd","properties":{"description":"Lam Research provides etch equipment"}},{"id":"e_wENorB2yJMzb","type":"PROVIDES_EQUIPMENT_FOR","sourceId":"n_FNqc3Rcs2U9V","targetId":"n_lmb6kT5QIK0T","properties":{"description":"Lam Research provides deposition equipment"}},{"id":"e_x3c0TpVADBJf","type":"PROVIDES_EQUIPMENT_FOR","sourceId":"n_GmVtLr1067-v","targetId":"n_bmaJ3kGme_cq","properties":{"description":"KLA provides inspection and metrology equipment for wafer testing"}},{"id":"e_Wo4VHfns7yfy","type":"PROVIDES_EQUIPMENT_FOR","sourceId":"n_VvR8_G16XiWn","targetId":"n_-NTH5w0N6xSc","properties":{"description":"TEL provides coater/developer equipment for photolithography"}},{"id":"e_OFtuIJ0cDi4B","type":"PROVIDES_EQUIPMENT_FOR","sourceId":"n_VvR8_G16XiWn","targetId":"n_pfomrDa8oYtd","properties":{"description":"TEL provides etch equipment"}},{"id":"e_bbGT8A9DAB6M","type":"USED_IN","sourceId":"n__sKPJhqMpzUJ","targetId":"n_MNHupChPrcl3","properties":{"description":"Silicon is the primary substrate material in wafer preparation"}},{"id":"e_QBRkkDBqgL4w","type":"PRODUCED_BY","sourceId":"n_oMAWJfokYYz1","targetId":"n_z1kKDbfxpUgX","properties":{"description":"SiO2 is produced by the Oxidation process"}},{"id":"e_74J7Ofn95z-t","type":"USED_IN","sourceId":"n_yKCa6KKlidl7","targetId":"n_-NTH5w0N6xSc","properties":{"description":"Photoresist is coated on wafers for photolithography pattern transfer"}},{"id":"e_uy_T-apcvCo2","type":"USED_IN","sourceId":"n_oSGWGfFn0kC5","targetId":"n_vWDzWZb3pTrr","properties":{"description":"Copper is the primary interconnect metal used in metallization"}},{"id":"e_Mx5k8h0em4Ve","type":"USED_IN","sourceId":"n_qLiLlSbxddBq","targetId":"n_HSn13am7kSrA","properties":{"description":"Silane is a primary precursor gas for CVD"}},{"id":"e_ssK1USIzfVbf","type":"USED_IN","sourceId":"n_0mb34d39utPP","targetId":"n__tan2DG0WFNb","properties":{"description":"Fluorine-based etchants (CF4, SF6) used in dry etching of silicon and SiO2"}},{"id":"e_xvMSb4H121hm","type":"USED_IN","sourceId":"n_LETJSJQTIFq6","targetId":"n__tan2DG0WFNb","properties":{"description":"Chlorine-based etchants (Cl2, BCl3) used in dry etching of metals"}},{"id":"e_aZjqs8zdhH-G","type":"USED_IN","sourceId":"n_CSj9ynuSx88I","targetId":"n_REw7AnTtUDcG","properties":{"description":"SiGe is used in GAAFET nanosheet structures for strain engineering"}},{"id":"e_7AgPVVNYpq7n","type":"USED_IN","sourceId":"n_djF4CuPp7RDX","targetId":"n_pufyoer4s25B","properties":{"description":"High-k dielectrics (HfO2) used as gate dielectric in FinFET and newer transistors"}},{"id":"e_18Na1PSC1v15","type":"MANUFACTURES_AT","sourceId":"n_J7A8W6zPDREw","targetId":"n_TqwmAcZtu2QL","properties":{"description":"TSMC manufactures at 3nm node (N3 FinFET, 2022)"}},{"id":"e_HSJWtj60GNqT","type":"MANUFACTURES_AT","sourceId":"n_J7A8W6zPDREw","targetId":"n_5HpKwEX3ekmU","properties":{"description":"TSMC manufactures at 2nm node (N2 GAAFET, 2025)"}},{"id":"e_po92IZNzZVFf","type":"MANUFACTURES_AT","sourceId":"n_6StRjGGxeqRQ","targetId":"n_TqwmAcZtu2QL","properties":{"description":"Samsung manufactures at 3nm node (3GAA, 2022)"}},{"id":"e_p7TWwak3l8Y8","type":"MANUFACTURES_AT","sourceId":"n_6StRjGGxeqRQ","targetId":"n_5HpKwEX3ekmU","properties":{"description":"Samsung manufactures at 2nm node (SF2, late 2025)"}},{"id":"e_NvLIaDIU-fZk","type":"MANUFACTURES_FOR","sourceId":"n_J7A8W6zPDREw","targetId":"n_ZTSzJ-ebtciO","properties":{"description":"TSMC is Apple's exclusive foundry partner"}},{"id":"e_XqWTL0YOL9QE","type":"MANUFACTURES_FOR","sourceId":"n_J7A8W6zPDREw","targetId":"n_DBJ0urA3VtIk","properties":{"description":"TSMC is AMD's primary foundry partner"}},{"id":"e_zI0i89C-21HD","type":"OPERATES_AS","sourceId":"n_J7A8W6zPDREw","targetId":"n_g92FZR_HHS2u","properties":{"description":"TSMC operates as a pure-play foundry"}},{"id":"e_H9S4OlPDtbRJ","type":"OPERATES_AS","sourceId":"n_QlZFfoES8c-u","targetId":"n_tF3-jEypq7hB","properties":{"description":"Intel operates as an IDM"}},{"id":"e_XyL5HcNsypBu","type":"OPERATES_AS","sourceId":"n_TX847Of2SeJs","targetId":"n_QPDGTJ9l2Wtc","properties":{"description":"ASE Group operates as an OSAT provider"}},{"id":"e_wHSC6kGnGKa4","type":"SUCCESSOR_OF","sourceId":"n_1pf530zOO_h4","targetId":"n_uuYLPx8y0H-M","properties":{"description":"5nm node succeeded 7nm node"}},{"id":"e_hRUT3xONCtH0","type":"SUCCESSOR_OF","sourceId":"n_TqwmAcZtu2QL","targetId":"n_1pf530zOO_h4","properties":{"description":"3nm node succeeded 5nm node"}},{"id":"e_yfx10NjTbBsT","type":"SUCCESSOR_OF","sourceId":"n_5HpKwEX3ekmU","targetId":"n_TqwmAcZtu2QL","properties":{"description":"2nm node succeeded 3nm node"}},{"id":"e_SfRChBT99ge1","type":"SUCCESSOR_OF","sourceId":"n_Qy0MAHKWfUix","targetId":"n_5HpKwEX3ekmU","properties":{"description":"Sub-2nm / Angstrom era succeeds 2nm node"}},{"id":"e_qK9idh2vWsl2","type":"REQUIRES","sourceId":"n_uuYLPx8y0H-M","targetId":"n_rt3mYOzNV_mk","properties":{"description":"7nm node was first to require EUV lithography"}},{"id":"e_c9ppHm7JP6xk","type":"REQUIRES","sourceId":"n_Qy0MAHKWfUix","targetId":"n_PPPc4s3RDj0j","properties":{"description":"Sub-2nm nodes require High-NA EUV lithography"}},{"id":"e_bsQbPIGURoRh","type":"USES_TRANSISTOR","sourceId":"n_uuYLPx8y0H-M","targetId":"n_pufyoer4s25B","properties":{"description":"7nm node uses FinFET transistor architecture"}},{"id":"e_j3ume7iQrINk","type":"USES_TRANSISTOR","sourceId":"n_5HpKwEX3ekmU","targetId":"n_REw7AnTtUDcG","properties":{"description":"2nm node uses GAAFET transistor architecture"}},{"id":"e_lx1FDX3QHcQh","type":"USES_TRANSISTOR","sourceId":"n_Qy0MAHKWfUix","targetId":"n_tor6YhdUgK_T","properties":{"description":"Sub-2nm nodes expected to use CFET transistor architecture"}},{"id":"e_-Q9yTkCMjKor","type":"TECHNIQUE_OF","sourceId":"n_2ZHsneCXHzIa","targetId":"n_h7HMcZglsMjr","properties":{"description":"Wire bonding is a packaging technique"}},{"id":"e_3IaH34TzznXJ","type":"TECHNIQUE_OF","sourceId":"n_rv6vr2ljvNqW","targetId":"n_h7HMcZglsMjr","properties":{"description":"Flip chip is a packaging technique"}},{"id":"e_J433G5GCwtxo","type":"TECHNIQUE_OF","sourceId":"n_vP0lE-sIUcmE","targetId":"n_h7HMcZglsMjr","properties":{"description":"2.5D packaging is an advanced packaging technique"}},{"id":"e_BycRY2QfkmRg","type":"TECHNIQUE_OF","sourceId":"n_wT22RZ2AWhNE","targetId":"n_h7HMcZglsMjr","properties":{"description":"3D packaging is an advanced packaging technique"}},{"id":"e_QhPW79GQTqKB","type":"ENABLES","sourceId":"n_tR9WmbjomEui","targetId":"n_wT22RZ2AWhNE","properties":{"description":"Hybrid bonding enables 3D packaging with sub-10um pitch"}},{"id":"e_EE3Wf2Za9qoG","type":"ENABLES","sourceId":"n_75YQN8G1UadR","targetId":"n_vP0lE-sIUcmE","properties":{"description":"Chiplet architecture typically uses 2.5D packaging"}},{"id":"e_cJfaZjYnE7Uy","type":"TECHNIQUE_OF","sourceId":"n_r1q8Ke2fyK9s","targetId":"n_bmaJ3kGme_cq","properties":{"description":"Optical inspection is a metrology technique used in wafer testing"}},{"id":"e_P58z1DyOXfiF","type":"TECHNIQUE_OF","sourceId":"n_U2-ZT79svbJ7","targetId":"n_bmaJ3kGme_cq","properties":{"description":"E-beam inspection is a metrology technique used in wafer testing"}},{"id":"e_olxoYXDe3o2W","type":"TECHNIQUE_OF","sourceId":"n_Uo5jND18Bxra","targetId":"n_bmaJ3kGme_cq","properties":{"description":"Scatterometry (OCD) is a metrology technique used in wafer testing"}},{"id":"e_tiWDMYnI5TII","type":"GOVERNED_BY","sourceId":"n_9tEU1emzCl6v","targetId":"n_rBfosr3gqIGZ","properties":{"description":"Semiconductor fabs are governed by ISO 14644-1 cleanroom standards"}},{"id":"e_BoUgsglragDM","type":"PERFORMED_IN","sourceId":"n_-NTH5w0N6xSc","targetId":"n_9tEU1emzCl6v","properties":{"description":"Photolithography is performed in a semiconductor fab cleanroom"}},{"id":"e_Rdmykc_yfiHU","type":"COMPLEMENTS","sourceId":"n_QA79JhsG_ycr","targetId":"n_Tctx18kbrk8n","properties":{"description":"Ion implantation (shallow junctions) complements diffusion (deep junctions)"}},{"id":"e_5Rd5ryQxdKXR","type":"DESIGNS","sourceId":"n_ZTSzJ-ebtciO","targetId":"n_8swsPTpSCTEN","properties":{"description":"Apple designs custom SoCs (A-series, M-series)"}},{"id":"e_tT2ttBeAvCXV","type":"DESIGNS","sourceId":"n_IH1MmaoZXgaY","targetId":"n_DjIHxI3jj3C0","properties":{"description":"Texas Instruments designs analog ICs"}},{"id":"e_VWXcMGlRRdNo","type":"TECHNIQUE_OF","sourceId":"n_Dqsg-ApIliOR","targetId":"n_h7HMcZglsMjr","properties":{"description":"Fan-out wafer level packaging is an advanced packaging technique"}}]}